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This diagram shows the timing and decoding associated with communication over the serial port. The first circuit allows for a reset of the timing sequence that parses the RS232 signal and uses the a not gate to clear the counter when the signal goes high which corresponds to a stop bit. As you can see, when the array of d flip-flops has written something to the final flop, the decoding is finished and the data_ready data\_ready  line goes high which enables the memory functionality discussed in Diagram 1.