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FPGA Lab 8
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layout.md
abstract.tex intro.tex circuits.tex figures/baud_clock1/baud_clock1.jpg figures/baud_clock/loopBack.jpg figures/attachingWire/attachingWire.JPG figures/ctrl_a/ctrl_a.JPG figures/ctrl_b1/ctrl_b1.JPG figures/ctrl_c3/ctrl_c3.JPG