Part 1 of this lab involved the implementation of a simple counter using a Quartus Megafunction. After hooking up the counter to the FPGA’s onboard clock, I tested that the counter worked as intended. Then, using Quartus’s simulation features, I was able to look at the individual logic states of the parts of my logic both by tying the line to an output line on the board as well as using registers which were able to provide byte level inspection at any location on the board. Using an iPhone, I was able to record the clock as it incremented. In the 10 seconds I recorded the counter, it incremented \(1.99\times10^9\) times which gives the clock a period of
\(\frac{10}{1.9\times10^9} = 50.25 MHz\)
Which is pretty close to the 50 MHz that is expected by the FPGA.
After timing the clock, I simulated its performance using the Quartus simulator and verified that the counter incrememented to the right value at the right time.
The 2\(^{nd}\) part of the lab involved the creation of a binary-coded decimal counter which was made out of 5 up counters with a modulus of 10 as described in Section 2.2. In order to drive the system every hundredth of a second, I connected the FPGA’s CLOCK_50 to a modulus 500000 counter whose cout went high at the desired frequency.
Part 3 of the lab involved the creation of a 4 bit counter from elementary gates and a D flop. I did use a Quartus megafunction in order to create a modulus counter that would drive the system every second. In constructing this diagram, I needed to create a 1 bit adder without a carry-in (done with an xor and and) 1 bit multiplexer (created with an inverter) which acts as the carry-in for the counter as a whole.