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The 2^{nd} part of the lab involved the creation of a binary-coded decimal counter which was made out of 5 up counters with a modulus of 10 as described in Section 2.2. In order to drive the system every hundredth of a second, I connected the FPGA's CLOCK\_50 to a modulus 500000 counter whose cout went high at the desired frequency.   Part 3 of the lab involved the creation of a 4 bit counter from elementary gates and a D flop. I did use a Quartus megafunction in order to create a modulus counter that would drive the system every second. In constructing this diagram, I needed to create a 1 bit adder without a carry-in (done with an xor and and) 1 bit multiplexer (created with an inverter) which acts as the carry-in for the counter as a whole.