<h2 id="auto-label-subsection-771002" class="ltx_title_subsection">Washington Nanofabrication Facility (WNF) silicon photonics process:<br></h2><div>The devices were fabricated using 100 keV Electron Beam Lithography [<cite class="ltx_cite" data-bib-text="@article{Bojko_2011,
	doi = {10.1116/1.3653266},
	url = {http://dx.doi.org/10.1116/1.3653266},
	year = 2011,
	publisher = {American Vacuum Society},
	volume = {29},
	number = {6},
	pages = {06F309},
	author = {Richard J. Bojko and Jing Li and Li He and Tom Baehr-Jones and Michael Hochberg and Yukinori Aida},
	title = {Electron beam lithography writing strategies for low loss,
high confinement silicon optical waveguides},
	journal = {Journal of Vacuum Science {\&amp;} Technology B: Microelectronics and Nanometer Structures}
}" data-bib-key="Bojko_2011" contenteditable="false"><a href="#Bojko_2011">Bojko 2011</a></cite>]. The fabrication used silicon-on-insulator wafer with 220 nm thick silicon on 3 μm thick silicon dioxide. The substrates were 25 mm squares diced from 150 mm wafers. After a solvent rinse and hot-plate dehydration bake, hydrogen silsesquioxane resist (HSQ, Dow-Corning XP-1541-006) was spin-coated at 4000 rpm, then hotplate baked at 80 °C for 4 minutes. Electron beam lithography was performed using a JEOL JBX-6300FS system operated at 100 keV energy, 8 nA beam current, and 500 µm exposure field size. The machine grid used for shape placement was 1 nm, while the beam stepping grid, the spacing between dwell points during the shape writing, was 6 nm. An exposure dose of 2800 µC/cm2 was used. The resist was developed by immersion in 25% tetramethylammonium hydroxide for 4 minutes, followed by a flowing deionized water rinse for 60 s, an isopropanol rinse for 10 s, and then blown dry with nitrogen. The silicon was removed from unexposed areas using inductively coupled plasma etching in an Oxford Plasmalab System 100, with a chlorine gas flow of 20 sccm, pressure of 12 mT, ICP power of 800 W, bias power of 40 W, and a platen temperature of 20 °C, resulting in a bias voltage of 185 V. During etching, chips were mounted on a 100 mm silicon carrier wafer using perfluoropolyether vacuum oil.<br></div>