deletions | additions       diff --git a/Bath Power System.tex b/Bath Power System.tex  index 85b6cc2..573df19 100644  --- a/Bath Power System.tex  +++ b/Bath Power System.tex 
...
Flash ADCs use a sequence of comparators and logic gates to facilitate an extremely fast conversion. Hhowever, the number of output bits, the number of logic gates and comparators needed increases exponentially because one comparator is needed for each discrete value. Therefore the cost implications of flash ADCs of >8bits are prohibitive for many applications.  Successive approximation ADCs use utilise  a comparator coupled with a digital-to-analogue converter to get a gradually more make increasingly  accurate digital value. Successive approximation ADCs take values over  a different amount series  of time to arrive at a digital value depending upon how many successive steps attempts. Because more attempts  are taken needed  to reach the correct convert different  analogue value. voltages, the conversion duration is not fixed.  These ADCs can be produced with much higher resolution,but  at lower the detriment of  sample rates. rate.  Sub-ranging ADCs use are a hybrid of flash and  successive approximation techniques to find the most approximtion ADCs. The more  significant bit values, bits are determined by a successive approximation technique,  and the lower bits converted by  a flash ADC to find technique. This gives  the least significant bits. ADCs some of the speed of an all-flash ADC, whilst retaining the resolution of successive approcimation ADCs  This allows sub-ranging ADCs to perform faster than successive approximation ADCs, but slower than flash ADCs. The ability to obtain the most significant bits by successive approximation allows these ADCs to have high resolution, without the vastly increased cost of purely flash ADCs.