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\title{The Design of HyperFETs}
\author{Sam Bader\\ Cornell University }
\maketitle
\section{Model}
\subsection{Transistor}
The transistor is modeled generically by a heavily simplified virtual-source (short-channel) MOSFET model \hyperref[csl:1]{[1]}. Although this model was first defined for Silicon transistors, it has been successfully adapted to numerous other contexts, including Graphene \hyperref[csl:2]{[2]} and Gallium Nitride devices, both HEMTs \hyperref[csl:3]{[3]} and MOSHEMT+VO$_2$ HyperFETs \hyperref[csl:4]{[4]}. Following Khakifirooz \hyperref[csl:1]{[1]}, the drain current $I_D$ is expressed
\begin{equation}
\frac{I_D}{W}=Q_{ix_0}v_{x_0}F_s
\end{equation}
where $Q_{iz_0}$ is the charge at the virtual source point, $v_{x_0}$ is the virtual source saturation velocity, and $F_s$ is an empirically fitted "saturation function" which smoothly transitions between linear ($F_s\propto V_{DS}/V_{DSSAT}$) and saturation ($F_s\approx 1$) regimes. The charge in the channel is described via the following semi-empirical form first proposed for CMOS-VLSI modeling \hyperref[csl:5]{[5]} and employed frequently since (often with modifications, eg \hyperref[csl:1]{[1]}; \hyperref[csl:3]{[3]}):
\begin{equation}
Q_{ix_0}=C_\mathrm{inv}nV_\mathrm{th}\ln\left[1+\exp\left\{\frac{V_{GSi}-V_T}{nV_\mathrm{th}}\right\}\right]
\end{equation}
where $C_\mathrm{inv}$ is an effective inversion capacitance for the gate, $nV_{th}\ln10$ is the subthreshold swing of the transistor, $V_{GSi}$ is the transistor gate-to-source voltage, $V_T$ is the threshold voltage, and $V_\mathrm{th}$ is the thermal voltage $kT/q$.
For precise modeling, Khakifirooz includes further adjustments of $V_T$ due to the drain voltage (DIBL parameter) and the gate voltage (strong vs weak inversion shift), as well as a functional form of $F_s$. For a first-pass, we will ignore these effects, employ a constant $V_T$, and assume the supply voltage is maintained above the gate overdrive such that $F_s\approx 1$. However, we will add on a leakage floor with conductance $G_\mathrm{leak}$. Altogether, the final current expression (for the analytical part of this analysis) is
\begin{equation}
\frac{I_D}{W}=nv_{x_0}C_\mathrm{inv}V_{th}\ln\left[1+\exp\left\{\frac{V_\mathrm{GSi}-V_\mathrm{T}}{nV_{th}}\right\}\right]+\frac{G_\mathrm{leak}}{W}V_\mathrm{DSi}\label{eq:transistor_iv}
\end{equation}
\subsection{Phase-change resistor}
\label{ss:PCR}
The phase-change material is included by a similarly generic and brutally simple model. As done with the transistor, the goal is to capture only the most relevant feature: here, an abrupt change in resistance. However, for a concrete example, the material most frequently used in HyperFET research \hyperref[csl:6]{[6]}; \hyperref[csl:7]{[7]} is Vanadium Diozide (VO$_2$), which features an S-style (ie current-controlled) and hysteretic negative differential resistance (NDR) region \hyperref[csl:8]{[8]}; \hyperref[csl:9]{[9]} due to an insulator-metal transition (IMT), the underlying mechanism of which has been a source of long-running controversy \hyperref[csl:6]{[6]}. Though the literature contains numerous examples of voltage-swept I-V curves \hyperref[csl:7]{[7]}; \hyperref[csl:9]{[9]}; \hyperref[csl:10]{[10]}; \hyperref[csl:11]{[11]}, proper modeling of a current-controlled NDR device in a circuit requires a current-swept I-V, examples of which can be found in \hyperref[csl:9]{[9]}; \hyperref[csl:12]{[12]}; \hyperref[csl:8]{[8]}. The cleanest of these is Figure 1(b) of Kumar \hyperref[csl:12]{[12]}, which is suggested to the reader as a concrete realization of the model used herein.
The phase-change resistor (PCR) will be described by a hysteretic piecewise-linear model:
\begin{equation}
V_R=\left\{\begin{array}{llr}
I_RR_\mathrm{ins}&, & I_R < I_\mathrm{IMT}\\
V_\mathrm{met}+I_RR_\mathrm{met}&, & I_R > I_\mathrm{MIT}\\
\end{array}\right\}
\label{eq:PCR_iv}
\end{equation}
where we require $I_\mathrm{MIT}\le I_\mathrm{IMT}$ to ensure that the model is defined for all values of the current; $I_\mathrm{MIT}=I_\mathrm{IMT}$ would be the case of zero hysteresis. For convenience, we define voltage thresholds, $V_\mathrm{IMT}=I_\mathrm{IMT}R_\mathrm{ins}$ and $V_\mathrm{MIT}=I_\mathrm{MIT}R_\mathrm{met}+V_\mathrm{met}$. Finally, we require $V_\mathrm{met}+I_{IMT}R_\mathrm{met}V_\mathrm{MIT}$ to ensure that the absolute resistance of the metallic state is lower than that of the insulating state wherever they are both defined.
\section{HyperFET Regimes}
When the PCR is attached in series with the source of the transistor, the total device satisfies the above equations with the additional matching $I=I_D=I_R$ and $V_\mathrm{GSi}=V_{GS}-V_R$ where $I$ is the current through the device and $V_{GS}$ is the voltage between HyperFET gate (the transistor gate) and the HyperFET source (the exterior node of the resistor). We can immediately solve for several regions of the HyperFET model. For this section, it is assumed that the transistor and PCR are scaled such that the hysteretic region is entirely contained within subthreshold, and above the leakage floor; these choices will be discussed in the next section.
\subsection{Leakage floor}
When the transistor is completely off, only the leakage term of \eqref{eq:transistor_iv} remains, and combines with the PCR off-state resistance, leading to
\begin{equation}
I=G_\mathrm{off}V_{DS},\quad G_\mathrm{off}^{-1}=R_\mathrm{ins}+1/G_\mathrm{leak}
\end{equation}
\subsection{Insulating (lower) branch of hysteretic region}
For the lower branch (in the region above the leakage floor), we plug $V_\mathrm{GSi}=V_\mathrm{GS}-IR_\mathrm{ins}$ into the transistor I-V \eqref{eq:transistor_iv}, and take the subthreshold limit: $\ln(1+e^x)\approx e^x$ for $-x \gg 1$.
\begin{equation}
\frac{I}{W}=nC_\mathrm{inv}v_{x_0}V_{th}\exp\left\{\frac{V_\mathrm{GS}-IR_\mathrm{ins}-V_\mathrm{T}}{nV_{th}}\right\}
\label{eq:insbranch_preW}
\end{equation}
This can be rearranged and solved in terms of the Lambert $\mathcal{W}$ function
\begin{equation}
I=\frac{nV_{th}}{R_\mathrm{ins}}\mathcal{W}\left[WC_\mathrm{inv}v_{x_0}R_\mathrm{ins}\exp\left\{\frac{V_\mathrm{GS}-V_\mathrm{T}}{nV_{th}}\right\}\right]
\label{eq:insbranch}
\end{equation}
\subsection{Metallic (upper) branch of the hysteretic region}
For the upper branch, we plug in $V_\mathrm{GSi}=V_\mathrm{GS}-V_\mathrm{met}-IR_\mathrm{met}$, and follow the same procedure to find
\begin{equation}
I=\frac{nV_{th}}{R_\mathrm{met}}\mathcal{W}\left[WC_\mathrm{met}v_{x_0}R_\mathrm{met}\exp\left\{\frac{V_\mathrm{GS}-V_\mathrm{met}-V_\mathrm{T}}{nV_{th}}\right\}\right]
\label{eq:metbranch}
\end{equation}
Note that if the metal-state resistance is small $IR_\mathrm{met}\ll nV_{th}$, we can approximate
\begin{equation}
\frac{I}{W}\approx nV_{th}C_\mathrm{met}v_{x_0}\exp\left\{\frac{V_\mathrm{GS}-V_\mathrm{met}-V_\mathrm{T}}{nV_{th}}\right\}
\end{equation}
\subsection{Voltage boundaries of the hysteretic region}
The leftmost point of the upper branch is defined by the minimum current below which no metallic-state solution can exist: $I=I_\mathrm{MIT}$. By \eqref{eq:PCR_iv}, $V_\mathrm{R}=V_\mathrm{MIT}$. Plugging this point into \eqref{eq:transistor_iv} and solving yields
\begin{equation}
V_\mathrm{left}-V_\mathrm{T}=V_\mathrm{MIT}+nV_{th}\ln\left[\exp\left\{\frac{I_\mathrm{MIT}}{nv_{x_0}WC_\mathrm{inv}V_{th}}\right\}-1\right]
\end{equation}
We have not yet made an assumption of subthreshold in the above equation, but if we do, we arrive at
\begin{equation}
V_\mathrm{left}-V_\mathrm{T}\approx V_\mathrm{MIT}-nV_{th}\ln\left[\frac{nv_{x_0}WC_\mathrm{inv}V_{th}}{I_\mathrm{MIT}}\right]
\label{eq:Vleft_sub}
\end{equation}
The rightmost point of the upper branch is defined by the maximum current beyond which no insulating state solution can exist: $I=I_\mathrm{IMT}$. By definition then, $V_\mathrm{R}=V_\mathrm{IMT}$. Plugging this point in
\begin{equation}
V_\mathrm{right}-V_\mathrm{T}=V_\mathrm{IMT}+nV_{th}\ln\left[\exp\left\{\frac{I_\mathrm{IMT}}{nv_{x_0}WC_\mathrm{inv}V_{th}}\right\}-1\right]
\end{equation}
where again, we have delayed the assumption of subthreshold until this point:
\begin{equation}
V_\mathrm{right}-V_\mathrm{T}\approx V_\mathrm{IMT}-nV_{th}\ln\left[\frac{nv_{x_0}WC_\mathrm{inv}V_{th}}{I_\mathrm{IMT}}\right]
\label{eq:Vright_sub}
\end{equation}
\subsection{Dimensions of the hysteresis}
The width of the hysteresis is then
\begin{equation}
V_\mathrm{right}-V_\mathrm{left}=V_\mathrm{IMT}-V_\mathrm{MIT}+nV_{th}\ln\left[\frac{I_\mathrm{IMT}}{I_\mathrm{MIT}}\right]
\end{equation}
\section{Application toward digital logic}
Given the above expressions, we now analyze the effect of the PCR on $V_\mathrm{on}$ and $I_{on}/I_{off}$. We begin with some basic observations of the HyperFET I-V and how they shape the design space for a steep-switching device.
\begin{enumerate}
\item In all of the above, $V_\mathrm{GS}$ only ever appears in the combination $V_\mathrm{GS}-V_\mathrm{T}$, so a device engineer can shift the entire I-V curve horizontally by threshold-engineering, just as in a conventional transistor. Thus, we will assume, without loss of generality, that the HyperFET operates between 0V and $V_\mathrm{ON}$, and this range (of width $V_\mathrm{ON}$) can be shifted to any desired location on the HyperFET I-V curve.
\item If the HyperFET is to operate as a conventional logic device (with enhanced steepness), then the $V_\mathrm{OFF}=0\mathrm{V}$ must be to the left of the hysteresis, and $V_\mathrm{ON}$ must be to the right of the hysteresis. For a given PCR, this requires a minimum $V_\mathrm{ON}>V_\mathrm{hyst}=V_\mathrm{right}-V_\mathrm{left}$. From that minimum, $V_\mathrm{ON}$ will be expanded to ensure sufficient $I_\mathrm{ON}/I_\mathrm{OFF}$ ratio (unless this ratio is already satisfied at the boundaries of the hysteretic region).
\item Operation with
Given the ability to increase $\log\frac{I_\mathrm{ON}}{I_\mathrm{OFF}$ and $V_\mathrm{ON}$
Operating the device with $V_\mathrm{left}=0$, $V_\mathrm{ON}=V_\mathrm{right}$.
\item
\item If it is necessary to expand $V_\mathrm{ON}$ beyond $V_\mathrm{right}-V_\mathrm{left}$, should the operating range expand to the right or to the left of the hysteresis? From \eqref{eq:insbranch_preW}, we see that the HyperFET curve to the left of the hysteresis approaches the original
If the OFF point (0V) is too far from the
\end{enumerate}
The procedure is essentially to choose a desired $I_\mathrm{on}/I_\mathrm{off}$, then find the minimum $V_\mathrm{on}$ compatible with this choice, given a fixed PCR. We will assume that the device engineer is free to manipulate the $V_\mathrm{T}$ of the transistor, so that, effectively, the OFF point can be placed anywhere on the HyperFET I-V, and then the component devices are scaled.
sliding it left and right to choose where on the HyperFET I-V the OFF current ($V_\mathrm{GS}=0$) on the as necessary to optimize the design. Second, the device engineer may scale the transistor
We assume the component devices have been scaled with the optimization of these parameters in mind.
Thoughts for the morning:
(1) Defend why want hysteresis in subthreshold
(a) To be able to climb toward right
(b) Does shape of hysteresis change at lower values?
(2) Derive Von at fixed Ion/Ioff. (width of hyst provided min Von, then grow at nVth*(Ion/Ioff- [Ion/Ioff]_hyst)
(a) could probably get a better expression for [Von versus (Ion/Ioff)] or at least (Ion/Ioff)hyst by dividing Eq 6 and [the skipped equation leading to Eq 8]. That seems more likely to yield a good result than messing with W functions.
(3) Mention in intro: Boltzmann only violated at one VGS per branch. This paper gives the connection between local violation and global properties of Ion/Ioff vs Von.
(4) Compute with right-end in sat. Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits
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\section*{References}\sloppy
\phantomsection
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\phantomsection
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\phantomsection
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