# FPGA Lab 7

AbstractLab 7 instructed me to build an 8-bit triangle-wave and sine-wave generator. After building the triangle-wave generator I designed a sine-wave generator by using the output of the triangle wave as the read address for a ROM block which had the appropriate values in order to generate a since wave over the correct period. This lab was extremely useful in demonstrating how one can use a ROM block in order to save data that needs to be reproduced at a later time, an extremely common task in designing complicated circuits.
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# Introduction

Lab 7 instructed me to design a signal generator capable of producing two different kinds of signals: triangle and sine. In order to construct the triangle generator, I used an updown counter which switched at the half period of the generated wave. the only challenged that I encountered while desinging this was to find a way to have the counter switch at a particular value. This was accomplished using an S/R flip flop. In order to have the triangle wave oscillate with a particular frequency, I connected the 5th bit of a counter which changes every $$2^5$$ clock cycles. For the 50 MHz clock driving the FPGA, this corresponded to a frequency of 1.3 KHz. I then was able to turn the triangle wave generator into a sine wave by connecting the output of the triangle wave to a ROM block which had the necessary values to generate it. As this lab was relatively short and the FPGA has an on board codec, there were not many obstacles that I encountered while designing this circuit. I was able to easily test my design by attaching the audio jack to an osciliscope and verifying the waveform.

# Circuits

Part 1 of the lab instructed me to design a triangle wave generator which produces a signal with a frequency of around 1 kHz. In order to do this, I used an up/down counter which increments when the updown pin is one and decrements with updown is low. By taking the output from the counter and connecting it to a decoder, I was able to have two different actions at different points of the count since it needs to count up to a particular value and then count down. By attaching the output of corresponding to data = 1 on the decoder, I can send the S/R Flip flop a set signal in order to have it read one. Then, when the counter hits 254, I set a reset signal to the S/R flip flop and cause the counter to decrement. The flip flop has a 1 clock cycle delay which would cause the counter to flip at a clock cycle past the half way point. In order to prevent this, I used pins 1 and 254 for the decoder output.