FPGA Lab 5


Lab 5 instructed us to design a stopwatch using the supplied FPGAs. The circuit needed to be able to increment every tenth of a second and track the number of minutes and hours that had passed. While I was instructed to make a three-state machine that is driven by one button that causes the timer to stop/stop/reset in that order. However, I implemented a two-state system and attached the reset functionality to a second button in order to reflect the design of stopwatches that I had encountered. This lab was very useful in demonstrating the steps that are involved when creating a complete circuit. This included designing state machines as well as importing modules previously defined as external libraries which are extremely common when designing circuits.


There were two main parts to the stopwatch: the controller which handled the state of the counters, and the counter itself. The main obstacle that I encountered while designing this circuit was to find a way to have the same button perform two different tasks. By implementing the controller using a finite state machine, I could easily trigger the transition between the various states off of the same input. Another difficulty I encountered was that the inputs were staying high longer than the transition time, causing two transitions to happen back to back. In order to prevent this, I attached the button to a positive edge trigger which only sent a short burst.

The counter was implemented using a series of decimal coded binary counters with appropriate modulus’s in order to cause the next counter to increment at 59 minutes rather than 99.

Circuits / Figures

The circuit built in this lab can be broken into two separate parts: the controller and the display. The controller is discussed in figure \ref{fig:control} and the display in figure \ref{fig:display}.

\label{fig:control} This diagram shows the part of the circuit that is responsible for the logic driving the counter. The core of the controller is the finite state machine labeled stop in the diagram. The state machine is responsible for causing the counter to begin counting from its current value as well as stopping the count. As shown in figure \ref{fig:fsm}, when the button goes high, the state machine switches between start and stop. In order to trigger the transition, the built in keys on the FPGA were hooked up a positive edge trigger which sent a short pulse to the state machine causing only a single transition 1. Since the keys on the FPGA are attached to built in debouncers, I did not have to bring one in from previous projects. The second button is attached to the clear of each counter and acts as a reset.

  1. If the pulse is too long then it will still be high when the transition occurs causing another one.