In section 1, I constructed a rising edge trigger and connected it to the push buttons on the FPGA. The rising edge trigger was achieved using an AND gate and a D-flop. Since the D-flop goes high on the rising edge, the delay of the AND gate lets the signal go high momentarily before the NOT causes it to go low. This enables the counter for a short time which allowed me to time the delay of the AND gate. The only real challenge in this design was figuring out a way to quickly turn off the signal after it had gone high, after some considerations, I realized any simple logic delay would work so long as it was compared to itself with an AND gate. The D-flops are used to synchronize the input with the board’s clock.
In section 2, I was instructed to design a circuit which would debounce the push-button. Since the value needed to stay constant for a particular amount of time, I needed some sort of feedback loop that would allow the output to transition to the next level when the time came. In order to do this I used the sequence debouncer submodule that was provided in the lab files. After altering the logic a bit, I was able to create a submodule that behaved as I needed and could have a third input, done, which would tell the debouncer that it was time to transition.
Section 3 showed me how one can create submodules in Quartus. I created two different submodules, the debouncer and the positive edge trigger, and re-implemented the circuit I designed in section 2 using them. Doing this allows me to reuse these components in future circuits which require a positive edge trigger or a debouncer, two extremely useful components of complicated circuits.