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\begin{document}

\title{A Computationally Efficient Compact Model for Ferroelectric FinFETs
Switching with Asymmetric Non-Periodic Input Signals}



\author[1,1]{Shubham Sahay }%
\author[2]{Amol Gaidhane }%
\author[2]{Yogesh
Singh Chauhan }%
\author[2]{Raghvendra Dangi }%
\author[2]{Amit Verma }%
\affil[1]{Indian Institute of Technology Kanpur}%
\affil[2]{Affiliation not available}%


\vspace{-1em}



  
  \date{May 27, 2024}


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\begin{abstract}
In this paper, we develop a Verilog-A implementable compact model for
the dynamic switching of ferroelectric Fin-FETs (Fe-FinFETs) for
asymmetric non-periodic input signals. We use the multi-domain Preisach
Model to capture the saturated P-E loop of the ferroelectric capacitors.
In addition to the saturation loop, we model the history dependent minor
loop paths in the P-E by tracing input signals' turning points. To
capture the input signals' turning points, we propose an R-C circuit
based approach in this work. We calibrate our proposed model with the
experimental data, and it accurately captures the history effect and
minor loop paths of the ferroelectric capacitor. Furthermore, the
elimination of storage of each turning point makes the proposed model
computationally efficient compared with the previous implementations. We
also demonstrate the unique electrical characteristics of Fe-FinFETs by
integrating the developed compact model of Fe-Cap with the BSIM-CMG
model of 7nm FinFET.%
\end{abstract}%



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