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\begin{document}

\title{Power Management to Meet Thermal Safe Power in Fault-Tolerant Embedded
Systems}



\author[1]{Mohsen Ansari }%
\author[1]{Sina Yari-Karin }%
\author[1]{Sepideh Safari }%
\author[1]{Alireza Ejlali }%
\affil[1]{Affiliation not available}%


\vspace{-1em}



  
  \date{May 22, 2024}


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\begin{abstract}
Thermal Design Power (TDP) as the chip-level power constraint for a
specific chip has been exploited in fault-tolerant embedded systems.
TDP, as the chip-level power constraint of the system, could be either
pessimistic or thermally unsafe. Employing TDP as a pessimistic
constraint can increase the rate of missing real-time constraints
because of triggering Dynamic Thermal Management (DTM) more frequently.
If TDP as a chip-level power constraint is not a pessimistic constraint,
TDP can be thermally unsafe and can lead to thermal violations.
Employing Thermal Safe Power (TSP) as the core-level power constraint,
which is defined as a function of the number of simultaneously operating
cores, can result in improving the efficiency and the schedulability.
This comment improves the efficiency and the schedulability rate of one
of the proposed methods in the literature by employing TSP.%
\end{abstract}%



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