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\begin{document}

\title{Fast Power Density Aware 3D-IC Floorplanning for Hard Macro-Blocks Using
Best Operator Combination Genetic Algorithm}



\author[1]{Naorem Yaipharenba Meitei}%
\author[1]{Krishna Baishnab}%
\author[2]{Gaurav Trivedi}%
\affil[1]{National Institute of Technology Silchar}%
\affil[2]{Indian Institute of Technology Guwahati}%


\vspace{-1em}



  
  \date{May 29, 2024}


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\begin{abstract}
In this article, we propose a fast 3D-IC floorplanning method for hard
macro-blocks that includes a thermal management scheme. It applies a
genetic algorithm constituted by an optimal combination of crossover and
mutation operations to identify the optimal solution for design
variables, namely, total wire length, number of through-silicon vias
(TSVs), and maximum average layer power density. The proposed method
additionally makes use of a unique TSV placement scheme that arranges
TSVs next to their respective functional blocks. To enable efficient
heat transmission to the ambient environment, layers with higher power
densities are placed closer to the heat sink. The proposed 3D-IC
floorplanning approach provides the fewest TSVs, the lowest peak
temperature, and promising values of wire length within the least amount
of computation time. Compared to the recent fast thermal analysis for
fixed-outline 3D-floorplanning, it generates 13.14\% shorter wire
length, 39.27\% lower peak temperature, and 34.35\% lesser number of
TSVs on average with significant improvement in computation time, while
analyzing GSRC thermal benchmark circuits.%
\end{abstract}%



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