Abstract
In this letter, a low-voltage passive first-order noise shaping
charge-redistribution successive approximation register (SAR) ADC with
energy-efficient switching method is proposed. The energy-efficient
switching method is achieved by one-side switching instead (OSSI) method
and higher-bit switching instead (HBSI) method. The architecture is
modified to realize the noise-shaping loop properly. We present a
passive integrator with a dynamic DC offset to address the path gain
error from the varying voltage on the capacitor array at each
quantization step. Simulation results on a 180nm CMOS technology
operated at 0.6V supply and 25kHz sampling rate show 130nW power
consumption with a peak SNDR of 70.3dB.