The High-Voltage Level Shifter with dV/dt noises Shielding
Jianwen Cao, Ze-kun Zhou*, and Bo Zhang
University of Electronic Science and Technology of China, State Key Laboratory of Electronic Thin Films and Integrated Devices, Chengdu 610054, China
*Email: zkzhou@uestc.edu.cn
This paper proposes a HV (high-voltage) level shifter to shield thedV/dt noise. When there is the dV/dt noises, the proposed level shifter’s output is locked by the dV/dt noise shielding circuit. So, the proposed level shifter has infinite dV/dtimmunity, which is not affected by the supply voltage, and processes. In the 0.5µm BCD process, the proposed level shifter is simulated, realizing the ±250V/ns dV/dt noises shielding function and less than 1.5ns delay time under the 400V HV power supply.
Introduction: With the development of wide-bandgap power MOSFET in HV (high-voltage) applications, high-performance gate drivers are required [1-3]. HV and high-speed gate drivers are also essential in wide-bandgap power MOSFET applications due to high-frequency applications [1]. At the same time, for wide-bandgap power MOSFET’s driving circuit, the synchronous gate driver is often designed on the chip to improve the system efficiency [1]. However, the largedV/dt noise generated by power devices could introduce and interfere with the synchronous gate driver. Therefore, as the critical sub-block of gate drivers, the level shifter has a high dV/dtimmunity requirement in wide-bandgap applications. The existing HV level shifters use many design techniques to improve dV/dt immunity [1-4]. These level shifters’ dV/dt noise immunity has been significantly enhanced, about hundreds of V/ns. In [3], a 200V/nsdV/dt noise immunity is achieved using the capacitive level shifter in the SOI process with a 200V power supply, which is limited by the process. For most level shifters in conventional processes, thedV/dt noise has a greater influence on the level shifter with the increase of supply voltage. Then, circuits that have been to enhancedV/dt immunity and need more energy to suppress dV/dtnoise. Therefore, the existing design methods to improve level shifter immunity could gradually become unavailable with the increase of power supply voltage. This paper proposes the HV floating level shifter withdV/dt noises shielding function. The core mechanism is that whendV/dt noise occurs, the proposed level shifter locks the output to prevent it from triggering by mistake.
The dV/dt noise interference to HV level shifters: There are two situations for the HV floating level shifter disturbed by dV/dtnoises. The HV floating power supply rail rises synchronously, which is the positive dV/dt noise; the other is that the HV floating power supply rail falls synchronously, which is the negative dV/dtnoise. Therefore, only the circuit connected with both HV and LV regions needs to be considered when the level shifter is disturbed bydV/dt noises, as described in [4]. For the HV floating level shifter, HV and LV regions have the same power supply rail voltage [4]. VDDH-VSSH is equal to VDDL-VSSL, and the LV power supply rail (VDDL-VSSL) is fixed.
Fig. 1 The positive dV/dt noise interference.
Fig. 2 The negative dV/dt noise interference.
When IN is high, the level shifter is interfered with by the positivedV/dt noise, as shown in Fig. 1. When IN is high, VA is equal to VSSH, and VB is equal to VDDH. When the positive dV/dt noise comes, VSSH and VDDH rise synchronously, and nodes A and B also increase due to parasitic capacitance charging. The parasitic capacitance charging current is limited, so the rising speed of nodes A and B are relatively slow, especially for the level shifter without the dV/dt immunity improving circuit. Thus, VA-VSSH and VB-VSSH could decrease when the positive dV/dtnoise happens. Owing to M7’s body diode, VA-VSSH could be clamped down to -VF. The high-level VB-VSSH may become a low-level signal and clamped to -VF due to M8’s body diode, as shown in Fig. 1(b). VF is the forward voltage of MOSFET’s body diode.
When the negative dV/dt noise occurs, both VA-VSSH and VB-VSSH could increase, as shown in Fig. 2. The analysis is similar to the above. When IN is high, and the negative dV/dt noise occurs, nodes A and B become high. Of course, each node voltage is within the allowed range due to the MOSFET’s parasitic diode.
The proposed level shifter with dV/dt noises shielding: According to the above dV/dt noise interference analysis, when IN is high and VSSH and VDDH rise synchronously, both VA-VSSH and VB-VSSH have an undershoot. Nodes A and B could become low. When IN is high and VSSH and VDDH fall synchronously, both VA-VSSH and VB-VSSH have an overshot. Nodes A and B could become high. When there is no dV/dt noise, VA and VB are opposite. For example, IN is high, node A is low, and node B is high. Therefore, nodes A and B have different voltage changes in normal operation and dV/dtnoises interference. Utilizing the differences analyzed above, the level shifter with dV/dt noises shielding function is proposed, as shown in Fig. 3.
The proposed level shifter’s transient operating is illustrated through a low-to-high operation. When IN goes high, M1 and M3 are turned on, and M2 and M4 are turned off. Nodes A and C start going down. Then, node A’s falling edge is sampled, and MH1 is turned on to accelerate node B’s rising. After node A drops, NAND2 outputs a high signal R. At this time, node A is low and INV1 outputs a high signal. When node B is higher than the NAND1’s triggering voltage, NAND1 outputs a low-level signal S. Finally, Latch outputs a high signal OUT. This is the low-to-high transient operation of the proposed level shifter, as shown in Fig. 4 (a). The high-to-low transient operation of the proposed level shifter is similar to the above operation.
As can be seen in Fig. 3 and Fig. 4 (a), when IN is high, due to the huge pull-down ability of M1 and M3, node A drops rapidly, while node B rises slowly. Therefore, the auxiliary pull-up transistors MH1 and MH2 are added to improve the proposed level shifter’s response speed, as shown in Fig. 3.
The proposed level shifter can shield the dV/dt noise using logic gates (INV1/INV2 and NAND1/NAND2). According to the above analysis, only when the voltages of nodes A and B are different, S or R of Latch could become low. That is, the proposed level shifter starts to transfer the input signal IN to the output signal OUT. When the dV/dt noise occurs, nodes A and B have the same voltage variation trend. When thedV/dt noise is small, the voltage variation of nodes A and B cannot be higher than the logic gate’s trigger voltage. Then, the output of NAND1 and NAND2 remains unchanged and OUT also keeps constant. When the dV/dt noise is large, the voltage variation of nodes A and B is higher than the logic gate’s trigger voltage. At this time, nodes A and B have the same variation. Due to using INV1/INV2, NAND1/NAND2 could output a high signal, and the output of Latch remains unchanged. So, the output OUT of the proposed level shifter remains constant and is not disturbed by dV/dt noise.
Fig. 3 The proposed level shifter with dV/dt noise shielding function.
Fig. 4 The waveform of the proposed level shifter, (a) the low-to-high operation, (b) dV/dt noises shielding function when IN is high.
For example, Fig. 4 (b) shows the proposed level shifter’s waveform during shielding positive and negative dV/dt noises. When IN is high, VA-VSSH is low and VB-VSSH is equal to VDDL. When the negative dV/dt noise comes, VA-VSSH and VB-VSSH rise. VB-VSSH does not exceed VDDL+VF due to the M8’s body diode. In this situation, VB-VSSH is always higher than the INV2’s triggering voltage and VRalso keeps high. The variation voltage of VA-VSSH is ΔVA. When ΔVA is lower than INV1’s triggering voltage, VS remains low. Then, OUT is still high. When ΔVA exceeds the INV1’s triggering, VS becomes high. Two inputs of Latch are high, so OUT remain high. When the positive dV/dt noise comes, the operation is similar to the above.
Therefore, when IN is high, the proposed level shifter’s output OUT always remains unchanged whether any dV/dt noises happens. Then, the proposed level shifter realizes the dV/dt noise shielding function. When IN is low, a similar situation also happens. Therefore, the proposed level shifter detects nodes A and B’s voltage variation by logic gates INV1/INV2 and NAND1/NAND2 to determine whether there are large dV/dt noises. The proposed level shifter can shield thedV/dt noise from disturbing the output OUT.
The proposed level shifter is simulated under a 0.5µm BCD process. VSSH is 400V, and VDDL is 5V. Fig. 5 simulates the proposed level shifter’sdV/dt noise shielding function at the ±250V/ns dV/dtnoise. The simulation result shows that nodes A and B have the same voltage variation due to dV/dt noise, while input signals S and R of Latch only appear high. Therefore, the proposed level shifter’s output OUT could not be disturbed by dV/dt noises. This can illustrate that the proposed level shifter has a shielding function todV/dt noise, which is also suitable for other power supply voltages and processes. Fig. 6 is the simulation result of the proposed level shifter’s rising and falling delay, realizing a 1ns rising and 1.4ns falling delay time under a 400V power supply.