However, the achievable conductance range and operating conditions such as speed and voltage seemed to be strongly and sensitively correlated to the materials and geometry of each layer. Therefore, it is important to consider and design a material aimed at specific applications such as defining the required array size and implementing appropriate drive circuitries. Moreover, similar to the challenge of the interface-type RRAM, the ECRAM required a long pulse to drive ions through the entire area. Although the operation was demonstrated in less than 10 ns, the tunable conductance range became very short as a result of a trade-off relation.
Ferroelectric Memory/MRAM
When the device structure is not limited to the compact two-terminal structure, it is expected that highly uniform and reliable synaptic characteristics will be achieved by exploring domain switching dynamics in ferroelectric (or magnetic) materials instead of the ion migration that accompanies the inevitable inherent stochasticity. As the voltage is applied to the ferroelectric oxides such as PbZrTiO
3 or SrBiTa
2O
5, the dipoles in the material begin to be rotated.
[33] The orientation of the dipoles aligned in a similar direction allows a spontaneous polarization and holds the state even when the voltage is removed. The ferroelectric material can directly be implemented to the gate dielectric of the transistor, resulting in ferroelectric field-effect transistor (FeFET).
[84] However, the complex ternary oxide systems require a substantial thickness (greater than 100 nm) to realize the ferroelectricity, making it difficult to integrate into the FeFET structure. The discovery of the ferroelectric behaviors in thin HfO
2 materials (less than 20 nm) has led to the renaissance of the ferroelectric memory toward the semiconductor industry
[85] To realize the ferroelectricity, it has been believed that phases of the HfO
2 film need to be transformed to a particular orthorhombic phase. Additional dopants such as Al, Zr, and Si have been proposed to facilitate structural evolution and stabilize the metastable phase, as well as high-temperature (or pressure) annealing as a driving force.
[86] Due to the use of the HfO
2 for the gate dielectric, a thinned ferroelectric layer that meets CMOS compatibility simultaneously enables the scaling potential to be regained. It was proved that the latest FeFETs have been demonstrated in 14
[87] and 28 nm
[39] technology nodes.
The FeFET operation is the similar to that of the FLASH memory. Applying positive gate voltage (
Vg) not only induces the channel inversion in the p-type silicon substrate as is normal but also causes spontaneous polarization in the ferroelectric gate dielectric that promotes the accumulation of electrons. Due to the ease of supply of sufficient electrons, the condition of creating an inversion layer is satisfied at a lower threshold voltage (
Vth) than that expected in the nFET. Meanwhile, the negative gate voltage switches the direction of the dipoles in the doped HfO
2 and negatively polarized charges induced near the channel, pushing electrons away. As the
Vth is shifted in the positive direction, the memory window in
Vth is exhibited. As the polycrystalline-doped HfO
2 comprised multiple ferroelectric domains, it was possible to be partially polarized, enabling fine-tuned threshold voltages.
[88, 89, 94, 95] Consequently, continuous channel conductance can be extracted from diverse traces of
Ids–
Vg of the FeFET. For the FeFET-based synapse, three available pulse schemes were evaluated. The identical pulse showed the gradual potentiation, whereas several states were only achieved due to a significant drop in the depression. By modulating the pulse width, the nonlinear response in the depression was improved. This is because the long pulse sufficiently converts the dipoles in the domain. Instead, the amplitude modulation scheme at a given pulse width of 50 ns increased the amount of the switched domains each time the pulse was applied, exhibiting the highest states (5-bit) and its symmetry. Due to the uniform synaptic behavior operated at a high speed, the neuromorphic system's performance indirectly verified by circuit-level macro simulators was discovered to have better accuracy of ≈90% on the MNIST and faster latency than other emerging memory-based synaptic candidates.
It has also been presented that the ferroelectric layer was implemented into more advanced transistor structures such as finFET
[90] and nanowire FET.
[91] Interestingly, both scaled FeFET-based synaptic devices seemed to have analogous conductance controlled by the identical pulse train. However, the linearity deviated from the ideal trajectory, which caused a reduced accuracy of ≈80% compared with that of the planar FeFET-based synapse (see Table
3).