Reversible logic has wide applications in the field of quantum computing, low-power design, nano-technology, optical information processing, bio-informatics etc. Due to the reversible nature of the circuit, it is conventionally easy to test the reversible circuit compared to irreversible circuit but it has its’ own complexity. In the recent years due to the scaling down of technology, bridging gate fault becomes more dominant. In this paper, we propose a polynomial time ATPG algorithm to generate complete test-set for all intra-level single and multiple bridging faults. This is the first approach in reversible state-of-art to test bridging faults using exact approach for the Reversible circuits designed with K-CNOT, PERES and FREDKIN gates.