• Efficient System Partitioning
• Very low latency (using 12 symbol transmissions
• Supports 3 traffic classes for simultaneous low latency and high bandwidth communication:
• Service (SVC)
• Low Latency (LL)
• Best Effort (BE)
• Minimal or no software housekeeping
• In-band signalling minimizes extra inter-chip General Purpose Input Outputs (GPIOs) and pin count
• Asymmetric M-PHY lanes implementation support reducing M-PHY link pins count
• HS- Gear 3 Support for MIPI M-PHY Physical Layer.
C. Core Frame Protocol this protocol is developed by PalmBeach corporation. The Core-Frame architecture is low power high-performance on-chip interconnect architecture for integration of SOC blocks.It consists of three independent parallel buses (CPU bus, Palm-Bus and M-Bus) rather than a hierarchy of buses which allows concurrent activities on both buses maximizing available bandwidth.
I. Palm-Bus represents a master-slave interface with a single-master intended for Communications between the CPU and peripheral blocks. It is not used to access memories. it is also designed with low-power consumption in mind.
II. M-Bus is designed for high-speed accesses to shared memory from the CPU core and peripheral blocks.
The most distinctive feature of the core-frame is the separation of the I/O and and memory transfers on different buses. The Palm-bus provides for the I/O back plane and allows the processor to configure and control while the M-bus provides a DMA connection from peripherals to main memory, allowing direct data transfer without processor intervention.