- Type (I) acts as a request-grant protocol. Only limited operation code and length are
supported.
- Type (II) This protocol is more efficient than type I as it supports split transactions
and adds pipelining features. The transaction set include read/write operation with different sizes (up
to 64 bytes) and also specific operations like read-modify-write and swap.
- Type (III) This is the most efficient protocol, as it adds support for split
transactions, out-of-order executions, and asymmetric communications. The switch or node is a block that arbitrates requests and responses, different kinds of arbitration
are possible, including fixed priorities and variable priorities. STBus can be implemented using different bus topologies as single shared bus, full crossbar and partial crossbar [7].
MIPI: Stands for Mobile Industry Processor Interface developed by MIPI Alliance. MIPI is the main interface for connecting IP blocks in mobile phone, A broad portfolio of interface specifications from the MIPI Alliance enables design engineers to efficiently interconnect essential components in a mobile device, from the modem and antenna to the peripherals and application processor. MIPI specifications have enabled manufacturers to simplify the design process, reduce design costs, create economies of scale that lower price points, and shorten time-to-market for components, features, and services. Fundamentally, every MIPI specification addresses the industry’s needs for three key characteristics that are essential for any successful mobile design: low power consumption, high-performance operations, and low electromagnetic interference (EMI). MIPI currently has a pair of high-speed physical-layer (PHY) specifications, M-PHY and D-PHY, to support a full range of application requirements in mobile terminals[4]. Application area for MIPI includes many domains, In this paper we focused on Chip-to-Chip Inter Process Communications which includes two main protocols LLI and DigRF.
- DigRF: DigRF is a high-speed digital interface standard defined and supported by the Mobile Industry Processor Interface (MIPI) Alliance. It is used primarily in between the RF transceiver IC and the baseband (BB) IC in a mobile handset. It provides a standard way to transmit I/Q data between the RF transceiver and the BB chip. The receiver circuits generate the I and Q signals from the radio signal. These are digitized and otherwise processed and sent to the BB circuits for further processing. In the transmit mode, the BB chip creates the digital versions of the I and Q signals and sends them to the RF chip over the interface. The RF chip performs digital-to-analog conversion to create the analog signals that become the radio signal to be transmitted. In the past, a variety of RF and BB chips generated both digital and analog I/Q signals. The DigRF interface standardizes digital transfers[5].
- LII: Stands for MIPI Low Latency interface, it is a point-to-point interconnection that allows two devices on separate chips to communicate as if a device attached to the remote chip is resident on the local chip. Devices on this bidirectional connection use memory mapped transactions for communications via native protocols such as Open Core Protocol and Advanced Microcontroller Bus Architecture (AMBA®), using the MIPI M-PHY® physical layer. As its primary use case, LLI targets concurrent low latency and high bandwidth chip-to-chip traffic over a low pin count interface, using any of three functionally oriented traffic classes: Service, Best Effort and Low Latency. Each provides an efficient mechanism for optimal data routing between the variety of devices supported by LLI[6].
- Core Frame Protocol:This protocol is developed by PalmBeach corporation. The Core-Frame architecture is low power high-performance on-chip interconnect architecture for integration of SOC blocks.It consists of three independent parallel buses (CPU bus, Palm-Bus and M-Bus) rather than a hierarchy of buses which allows concurrent activities on both buses maximizing available bandwidth.