C. PCI protocol standing for  Peripheral Component Interconnect. It is Used in connecting the elements of modern, high performance computer systems. It evolved when ISA bus failed to keep up with speed requirement  and the need to connect more than two devices to the VL-Bus which introduced the possibility of interference with the performance of the CPU , then PCI evolved which presents a hybrid of sorts between ISA and VL-Bus.
PCI provided direct access to system memory for connected devices and offers a number of significant advantages like speed and configurability . It is a synchronous bus with clock rate of 33 MHz and nowadays it is extended to support operation at 66 MHz and  implements a 32-bit multiplexed Address and Data bus where it could support a 64-bit data bus through a longer connector slot. The PCI bus speed is  independent of the CPU's speed and expansion of the bus could be achieved by means of a bridge. A PCI bus transfer is achieved through a set of data and address signals where it consists of one address phase and any number of data phases.