I. Processor Local Bus (PLB) :
-The PLB addresses the high performance, low latency and design flexibility issues needed in a highly integrated SOC through decoupled address, read data, and write data buses allowing concurrent read and write transfers thus maximising bus utilization also address pipelining that reduces bus latency by overlapping a new write request with an ongoing write transfer. PLB bus supports up to 16 master and any number of slaves.
- The PLB macro consists of a bus arbitration control unit and the control logic required to manage the address and data flow through the PLB. The separate address and data buses from the masters allow simultaneous transfer requests. The PLB macro arbitrates among these requests and directs the address, data and control signals from the granted master to the slave bus
- PLB bus transaction is grouped under an address cycle and a data cycle:
1-Address cycle: Master drives address and transfer qualifier signals (Request) Arbiter grants the bus ownership, presents the signals to the slave (Transfer) Slave latches the address and transfer qualifiers (Address-Acknowledge)
2-Data cycle: for each data beat, Master drives the write data bus for a write transfer or sample the read data bus for a read transfer (Transfer) , Data acknowledge signals are required after the beat.