The architecture consists of a backbone bus which has the capability to sustain the external memory bandwidth where the on-chip memory, CPU and other Direct Memory
AMBA is hierarchically organized into two bus segments, system and peripheral bus, mutually connected via bridge that buffers data and operations between them. AMBA does not define method of arbitration. Instead it allows the arbiter to be designed to suit the applications needs, the best.[19]
E.I. AMBA AHB
The AHB is mainly used for high-performance, high clock frequency system modules. It acts as the high-performance system backbone bus. It supports multiple bus masters, provides high-bandwidth operation and supports efficient connection of processors, off-chip external memory interfaces and on-chip memories with low-power peripheral macrocell functions. AHB Master, AHB Slave, AHB Arbiter, and AHB Decoder are the main components of the AHB.
AMBA AHB is a new level of bus which sits above the APB and implements the features required for high-performance, high clock frequency systems including:
- Burst transfers.
- Split transactions.
- Wider data bus configurations (64/128 bits).