Now,How data is transferred using in PCI protocol?
- PCI signals are active low, where PCI transaction is initiated when FRAME# signal is asserted low and hence the address phase is signaled .The next clock edge begins the first of one or more data phases in which data is transferred over the AD[31:0] signals.
- The initiator drives the C/BE[3:0]# which defines the type of transfer to be performed during the - address phase and during the data phase of a transaction these signals carry byte enable information.
IRDY# (Initiator Ready) is driven low by the initiator as an indication it is ready to complete the current data phase of the transaction , TRDY# (Target Ready )is driven low by the target as an indication it is read to complete the current data phase of the transaction. Only when both IRDY# and TRDY# are low transaction takes place.
- The initiator signals completion of the bus transfer by de-asserting the FRAME# signal during the last data phase.
- A target may terminate a bus transfer by asserting the STOP# signal. When the initiator detects an active STOP# signal, it must terminate the current bus transfer and re-arbitrate for the bus before continuing. If STOP# is asserted without any data phases completing, the target has issued a retry. If STOP# is asserted after one or more data phases have successfully completed, the target has issued a dis-connect.
- Initiators arbitrate for ownership of the bus by asserting a REQ# signal to a central arbiter. The arbiter grants ownership of the bus by asserting the GNT# signal. Arbitration in PCI is “hidden” in the sense that it does not consume clock cycles.
D. SATA stands for Serial Advanced Technology Attachment, its main application is to connect the host with the hard disk driver (HDD) or the solid state disk (SSD), The SATA environment is a point-to-point connection scheme (half-duplex). SATA uses 8b/10b encoding for clock recovery and DC balance and can transmit and recieve up to 6 Gb/sec differnetial NRZ serial stream. SATA standards do not define switches or other hardware mechanisms that allow the architecture to go beyond a single device to host connection. To overcome this restriction, the SATA community has defined a hardware and software scheme that will allow more than one (or two for ATA emulation) device to be attached to a host system. This is accomplished through a mechanism known as a Port Multiplier [9].
E. AMBA , Advanced Microcontroller Bus Architecture specification by ARM defines an on-chip communications standard which is required for designing high-performance embedded microcontrollers. AMBA comprises of three buses which are the Advanced High-performance Bus (AHB), the Advanced System Bus (ASB), the Advanced Peripheral Bus (APB), in addition to Advanced extensible Interface (AXI).