II. On-Chip Peripheral Bus(OPB): OPB is a secondary bus architected to reduce capacitive loading on the PLB, suitable for attachment of low-bandwidth devics . PLB masters gain access to the peripherals on the OPB bus through the OPB bridge. The bridge acts as a slave device on the PLB and a master on the OPB. The OPB supports multiple masters and slaves by implementing the address and data buses as a distributed multiplexer.
III. Device Control Register Bus : Lower performance status and configuration registers are typically read and written through the Device Control Register (DCR) Bus. The DCR provides a maximum throughput of one read or write transfer every two cycles. Fully synchronous bus typically implemented as a distributed multiplexer.
IV. SYSTEM ON CHIP BUSES; AUTOMOTIVE DOMAIN
In this section, We propose the main features of SoC buses provided in the industry. Given that the number of electronic components is increasing exponentially, point-to-point communication is not possible. The main reasons is the large number of wires needed to connect all the components, non-availability of space and in case of a failure the fault detection will be extremely difficult. As a result, serial buses as LIN, CAN , FLEXRAY for controlling and MOST for infotainment are discussed below.