I. INTRODUCTION
Shrinking process technologies and increasing design sizes have led to highly complex billion-transistor integrated circuits (ICs). As a consequence, manufacturers are trying to integrate large numbers of components on a chip. A heterogeneous system-on-a-chip (SoC) might include more no of programmable components such as general purpose processors cores, digital signal processor cores, or application specific intellectual property (IP) cores, as well as an analog front end, on-chip memory, I/O devices, and other application specific circuits. [1]
In CMOS SoC technology, due to rapidly increasing frequencies of operation and large chip size, On-chip bus based on Industry standards is among the top challenges. Usually, IP cores are designed with communication protocols and many different interfaces. Integration of such cores in a SoC often requires optimal logic. To avoid this problem, Standards of on-chip bus structures were developed [1]. Currently there are publicly available bus architectures from leading manufacturers, such as CoreConnect from IBM, AMBA from ARM, STBus from STMicroelectronics, and others. This paper focuses on multiple SoC protocols providing a comparative analysis of the main characteristics of the buses.
II. SYSTEM ON CHIP BUSES; COMPUTER DOMAIN
SoC Buses are classified into many categories based on the desired application. Every bus defines a set of signals, which utilizes “Master” and “Slave” architectures, connect to each other by interface called “INTERCON”. This “INTERCON” basically handle data transfer between Master and Slave IP Cores. Master start data transmission generating bus cycle, and sending address and control signal to Slave IP Core. Slave in turn receive bus cycle, so respond with specified address. SoC buses support different types of interconnection to interface Master and Slave. The interconnection includes Point to Point, Shared bus, Crossbar Switch, and Data Flow. In this paper we are going to focus on three main categories, each one will include a group of buses.
A. Wishbone is a SoC Bus which is commonly used in FPGA. Wishbone is a portable System on Chip design methodology. SoC design methodology interface wishbone bus, elevating integration problems and making SoC highly custom. Wishbone provide a portable interface to the IP Cores and use as an internal bus for SoC. The objective behind standard interface is to provide common interface between IP Cores improving portability, reliability of the system and faster time to market by end user. The wishbone bus accomplishes these objectives at single platform, Wishbone bus defines a set of signals and buses. Wishbone utilize “Master” and “Slave” architectures, connect to each other by interface called “INTERCON”. This “INTERCON” basically handle data transfer between Master and Slave IP Cores. Master start data transmission generating bus cycle, and sending address and control signal to Slave IP Core. Slave in turn receive bus cycle, so respond with specified address. Wishbone support four interconnection to interface Master and Slave. The interconnection includes Point to Point, Shared bus, Crossbar Switch, and Data Flow[2][3].