References

[1] Richard Herveille, WISHBONE System-on-Chip (SoC) Interconnection Architecture for Portable IP
Cores, rev. version: B4, 2010. By Open Cores Organization, p.7, 2010. www.opencores.org.
[2] Mohandeep Sharma and Dilip Kumar, WISHBONE Bus ARCHITECTURE – A SURVEY AND COMPARISON,Department of VLSI Design, Center for Development of Advanced Computing, Mohali,india,  at https://www.researchgate.net/publication/224926942.
[3]Altera Avalon, Avalon bus specification: Reference manual. Altera Corporation, July, 2003.
Available online at http://www.altera.com.
[4] MIPI alliance specifications, https://www.mipi.org.
[5] Luis Laranjeira, Synopsys ,MIPI DigRF 3G and MIPI DigRF v4 Solutions in Action, Member-to-Member Presentations March 9, 2011 by mipi alliance https://www.mipi.org.
[6] Low Latency  Interface (LLI) v2.1, Specification Overview, MIPI alliance,  7-Nov-2014,https://www.mipi.org.
[7]  STBus communication system concepts and definitions -  User manual provided by STMicroelectronics,  STMicroelectronics,  October 2012.
https://www.st.com/content/ccc/resource/technical/document/user_manual/39/81/fa/c8/2e/4d/41/f5/CD00176920.pdf/files/CD00176920.pdf/jcr:content/translations/en.CD00176920.pdf
[8]  David A. Deming, The Essential Guide to Serial ATA and SATA Express, 9 October 2014.