1. Bus masters assert AREQx during the HIGH phase of BCLK.2. The arbiter samples all AREQx signals on the falling edge of BCLK.3. During the LOW phase of BCLK the arbiter also samples the BLOK (lock signal) and then asserts the appropriate AGNTx signal:
- If BLOK is LOW, then the arbiter will grant the highest priority bus master
- If BLOK is HIGH, then the arbiter will keep the same bus master granted. [21]