1. MIPI LOW LATENCY: MIPI Low Latency Interface v2.1 is a point-to-point interconnect that allows two devices on separate chips to communicate as if a device attached to the remote chip is resident on the local chip. Devices on this bidirectional connection use memory mapped transactions for communications via native protocols such as Open Core Protocol and Advanced Microcontroller Bus Architecture (AMBA®), using the MIPI M-PHY® physical layer. As its primary use case, LLI targets concurrent low latency and high bandwidth chip-to-chip traffic over a low pin count interface, using any of three functionally oriented traffic classes: Service, Best Effort and Low Latency. Each provides an efficient mechanism for optimal data routing between the variety of devices supported by LLI, from direct HW-to-HW signaling and interrupts (using Service Traffic Class) to the high bandwidth, high volume data streams (bulk DMA transfers using Best Effort Traffic Class) to the occasional low bandwidth latency-critical transfers (cache refill traffic using Low Latency Traffic Class). Semantics of the Service Transaction signals are not specified and can be used for any purpose to reduce pin count on both sides of the link. LLI offers simultaneous support for multiple parallel communication flows in both directions for all three traffic classes without significant degradation in latency for low latency traffic and in bandwidth for best effort traffic and with independent transactions initiation from either side of the link. The LLI Specification describes a layered, transaction-level protocol, where Targets and Initiators on two linked chips exchange Transactions without software intervention. Software is used to initialize the LLI Stack at boot time, to manage errors handling, and to re-configure the LLI Link. This approach reduces latency and allows software compatibility regardless of the partitioning of the hardware on the two linked chips[6].