WISHBONE MASTER and SLAVE interfaces can be connected together in a number of ways. This requires that WISHBONE interface signals and bus cycles be designed in a very flexible and reusable manner. The signals were defined with the following requirements:
• The signals allow MASTER and SLAVE interfaces to support point-to-point, data flow, shared bus and crossbar switch interconnections.
• The signals allow three basic types of bus cycle. These include SINGLE READ/WRITE, BLOCK READ/WRITE and RMW (read-modify-write) bus cycles. The operation of these bus cycles is described below.
• A handshaking mechanism is used so that either the MASTER or the participating
SLAVE interface can adjust the data transfer rate during a bus cycle. This allows the
speed of each bus cycle (or phase) to be adjusted by either the MASTER or the SLAVE
interface. This means that all WISHBONE bus cycles run at the speed of the slowest interface.
• The handshaking mechanism allows a participating SLAVE to accept a data transfer, reject a data transfer with an error or ask the MASTER to retry a bus cycle. The SLAVE does this by generating the [ACK_O], [ERR_O] or [RTY_O] signals respectively. Every interface must support the [ACK_O] signal, but the error and retry acknowledgement signals are optional.
• All signals on MASTER and SLAVE interfaces are either inputs or outputs, but are never bi-directional (i.e. three-state). This is because some FPGA and ASIC devices do not support bi-directional signals. However, it is permissible (and sometimes advantageous) to use bi-directional signals in the interconnection logic if the target device supports it.
• Address and data bus widths can be altered to fit the application. 8, 16, 32 and 64-bit data buses, and 0-64-bit address buses are defined.
• As shown in figure (2) , all signals are arranged so that MASTER and SLAVE interfaces can be connected directly together to form a simple point-to-point interface. This allows very compact and efficient WISHBONE interfaces to be built. For example, WISHBONE could be used as the external system bus on a microprocessor IP Core. However, it’s efficient enough so that it can be used for internal buses inside of the microprocessor.
• User defined signals in the form of ‘tags’ are allowed. This allows the system integrator to add special purpose signals to each WISHBONE interface. For example, the system integrator could add a parity bit to the address or data buses.