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Elangovan M

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Static Random Access Memory (SRAM) occupies more than 50% of die area and becomes an important block in modern VLSI integrated circuits. The process variations with Metal Oxide Semiconductor (MOS) based SRAM cells in nanoscale range highly affect the functionality and may cause the data flip. The stability of SRAM cell is also degrading due to process variation. The MOS transistors reached its maximum efficiency in terms of their electrical conduction due to the reduction of device size in nanoscale range. The Carbon Nano Tube Field Effect Transistor (CNTFET)   has excellent properties like high conductivity in nanoscale range, good mechanical strength, and lightweight. Hence CNTFET would be the best alternative of MOS transistors for the future microelectronic circuit.  In this paper, we have proposed a highly stable and low power CNTFET based 8 Transistors (8T) SRAM cell. The performance of proposed 8T CNTFET SRAM cell is compared with that of conventional 6T and 8T CNTFET SRAM cells. From the simulation results, it is noted that the proposed structure consumes lesser power than conventional 6T and 8T CNTFET SRAM cells during write, hold and read operations. The proposed 8T CNTFET SRAM cell offers higher stability during writing and holds modes than conventional 6T and 8T CNTFET SRAM cells. The power performance and stability of proposed 8T CNTFET SRAM cell are observed for different parameters of CNTFET namely Dielectric constant (Kox), Oxide thickness (Hox), supply voltage, the Pitch value, and temperature. The power consumption and noise margin of proposed 8T CNTFET SRAM cell are compared with conventional 6T and 8T CNTFET SRAM cells. It is noted that during PVT variation also, the proposed 8T CNTFET SRAM cell gives good stability and consumes less power than conventional 6T and 8T CNTFET SRAM cells. Stability of A SRAM cell is measured through Read Static Noise Margin (RSNM), Write Static Noise Margin (WSNM) and Hold Static Noise Margin (HSNM). The power dissipation of the circuit is calculated for reading, write and hold modes. The simulation is carried out using the Stanford University 32nm CNTFET model.Keywords— SRAM, CNTFET, SNM and Process variation.