Item Name Rationale
Visibility Timestamp
Rationale for resolution (233ps): As a minimum each integration time needs to be uniquely identified therefore nanosecond timestamp resolution is needed for pulsar phase binning. Timestamp is sufficiently accurate to be used for all science without adding further precision (more than just accurate enough for identification of each integration period). The timestamp has been split into two SPEAD items to allow immediate addressing to be used which simplifies the implementation in FPGAs. Although this uses an additional 48bits compared to having the timestamp as a single SPEAD item, the effect on the data rate is negligible (refer to the overhead factor calculation).
Visibility Channel ID Channel ID requires at least 22 bits (for SKA2 #channels), therefore using a 32 bit unsigned integer. This fits into the SPEAD HeapAddressWidth (48bit) and allow immediate addressing.
Visibility Baseline ID Baseline ID requires at least 26 bits (for SKA2 and should including a polarisation ID be neccesary), therefore using a 32 bit unsigned integer. This fits into the SPEAD HeapAddressWidth (48bit) and allow immediate addressing.
Visibility Baseline Count Baseline Count requires at least 26 bits (same as baseline ID), therefore using a 32 bit unsigned integer. This fits into the SPEAD HeapAddressWidth (48bit) and allow immediate addressing.
Visibility Channel Count Channel Count requires at least 22 bits (for SKA2 #channels), therefore using a 32 bit unsigned integer. This fits into the SPEAD HeapAddressWidth (48bit) and allow immediate addressing.
Visibility Schedule Block ID Unsigned integer with size of SPEAD HeapAddressWidth (48bit). This should provide enough range for a unique schedule block ID, but needs to be confirmed with TM.
Visibility Hardware ID This indicates the hardware source of the data for testing/troubleshooting/back tracing to a hardware fault. How this variable is used has not been determined yet, in particular since the packets comprising a heap could be generated by multiple CSP Nodes. The size of the hardware ID (32bit) could be expanded to the SPEAD HeapAddressWidth (48bit) if needed.
Visibility Time Centroid
Rationale for precision of TCI is TBD Only 1 TCI and FD is required per baseline since the TCI and FD are identical for all polarisations due to SKA1-SYS_REQ-3538 (…flag all polarizations and polarization products if any are found to be bad.)
Complex Visibility Rationale for the precision of the complex visibility is TBD.
Visibility Flagging Fraction
SDP needs relatively more precision for low fractions. The weighting is based directly on the square root of the fraction. Only 1 TCI and FD is required per baseline since the TCI and FD are identical for all polarisations due to SKA1-SYS_REQ-3538 (…flag all polarizations and polarization products if any are found to be bad.)
Phase Bin ID and count Current the L1 reqs specify a maximum of 256 phase bins. CSP provide up to 1024 phase bins (SKA1-CSP_REQ-722). 16 bit unsigned integers were chosen for the ID and count as it provides enough range and fits into the SPEAD HeapAddressWidth (48bit).
Correlator output data Correlator output data (correlation products) per baseline. CSP prefers to keep the correlation products (TCI, FD, and visibilities) together for each baseline.