Figure 2.13: Binary to stochastic converter proposed using converters and NAND gates
It can be shown in Fig.2.13 that a circuit using simple logic elements such as: conveters and NAND gates to relize the logic function given in (2.14). There are also the number of PRNGs corresponding the number of bits using to represent the binary number x.
In oder to make an evaluation on this approach in comparison with Digital to Stochastic converter, an expected probability 0.625 (corresponding to x = 101 in binary encoding) will be generated. Like the implementation in the previous section, because of the number of bit representing the generating probability, three 10–LFSR–based PRNGs will be consequently investigated in this design.
The distribution and statistic parameters of this implementation when generating 10000 samples are illustrated in Fig.2.14. Based on the obtained results, this approach gives an acceptable in error evaluation and a good distribution nearly concentrating on expected probability. These results is also as good as one received from Digital to Stochastic converter (Fig.2.14) proposed by Brown and Card [4], and it seems a little better: the mean (0.6251)is closer to expected value, the parameters related to error is also smaller. These methods can be more faily compared when considering their hardware cost. Fig.2.15 illustrates an MUX including 2 ANDs, one NOT and one OR gates. Consequently,
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Figure 2.14: Histogram and statistic parameters of the output when using Variable probability generator to generate the expected probability 0.625