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Positive-to-negative tunable delay circuit designed with NGD RC network
  • +4
  • Shi Junwen,
  • Cui Junyan,
  • Hakim Epea Silochi,
  • Robert Wieser,
  • Raul Sanchez Galan,
  • Blaise Ravelo,
  • Nour Murad
Shi Junwen
Nanjing University of Information Science and Technology
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Cui Junyan
Nanjing University of Information Science and Technology
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Hakim Epea Silochi
Nanjing University of Information Science and Technology
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Robert Wieser
Nanjing University of Information Science and Technology
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Raul Sanchez Galan
Marie Curie Research Institute
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Blaise Ravelo
Nanjing University of Information Science and Technology
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Nour Murad
Universite de La Reunion IUT de La Reunion

Corresponding Author:[email protected]

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Abstract

Despite the performed progressive research work, the interpretation of negative group delay (NGD) function remains not familiar to non-specialist design and fabrication circuit engineers. The functionality misunderstanding limits the NGD circuit applications compared to other classical electronic functions. The present paper is dealing on the design of tunable property circuit by operating with positive and negative delay behaviors. The topology of the tunable circuit by using low-pass (LP) type NGD one is described. The design formulas for calculating the circuit resistor and capacitor parameters from the desired delay are expressed. The design feasibility of the tunable circuit composed of LP-NGD cell and RC-circuit is validated with a proof-of-concept (PoC) implemented on a test board. Two different signals with pulse and arbitrary waveforms having tens-milliseconds duration were considered during the validation tests. As expected by tuning a varistor from 0.4 kΩ to 1 kΩ, the negative delay behavior varying from about -0.4 ms was verified thanks to the time-advanced effect due to the LP-NGD property. Then, the output signal delay was observed to become positive when the varistor is tuned from 1 kΩ to 3 kΩ.
03 Nov 2023Submitted to International Journal of Circuit Theory and Applications
06 Nov 2023Review(s) Completed, Editorial Evaluation Pending
06 Nov 2023Assigned to Editor
06 Nov 2023Submission Checks Completed
08 Nov 2023Reviewer(s) Assigned