An Energy-Efficient Computing-in-Memory circuit based on
Multiplexing-Computing-Cell for BNN acceleration
This brief presents an energy-efficient Computing-in-Memory (CIM)
circuit based on novel Multiplexing-Computing-Cell. The proposed circuit
is capable of XNOR-and-accumulation (XAC) operations for binary neural
network (BNN). To reduce the delay and power consumption of the result
readout circuit, this circuit uses an all-digital adder tree circuit
based on an alternating structure of 11T full adder and 28T full adder.
This letter builds a 32Kb (512x64) size CIM circuit and achieves 98.3%
accuracy in MNIST dataset, with a latency of 3.5ns and an energy
efficiency of 56.4TOPS/W.