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A 0.9 V Wideband SPLL With an Adaptive Fast-Locking Circuit Achieving 24.68 μs Settling Time Reduction
  • Binghui Wang,
  • Shu Zhou,
  • Hai-Gang Yang
Binghui Wang
Chinese Academy of Sciences Aerospace Information Research Institute

Corresponding Author:[email protected]

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Shu Zhou
Nanyang Technological University School of Electrical and Electronic Engineering
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Hai-Gang Yang
University of the Chinese Academy of Sciences
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A low-power wideband self-biased phase-locked loop (SPLL) is proposed for multi-protocol SerDes applications in this letter. With the proposed adaptive fast-locking current circuit (AFLCC), the settling time is reduced significantly, and no extra power and jitter contribution. In addition, a start-up module is adopted to reset the system to an optimal initial operating frequency quickly. The proposed 1-3-GHz SPLL, fabricated in TSMC 28-nm CMOS process and occupies a compact 0.028mm2 area. It achieves a roughly constant settling time of 5 μs over all frequencies and division ratios range. Only 0.96 mW is consumed from a 0.9 V supply at 1 GHz frequency.
20 Mar 2023Submitted to Electronics Letters
20 Mar 2023Submission Checks Completed
20 Mar 2023Assigned to Editor
29 Mar 2023Reviewer(s) Assigned
06 May 2023Review(s) Completed, Editorial Evaluation Pending
08 May 2023Editorial Decision: Revise Major
08 Jun 20231st Revision Received
09 Jun 2023Submission Checks Completed
09 Jun 2023Assigned to Editor
09 Jun 2023Review(s) Completed, Editorial Evaluation Pending
14 Jun 2023Editorial Decision: Revise Minor
19 Jun 20232nd Revision Received
20 Jun 2023Submission Checks Completed
20 Jun 2023Assigned to Editor
20 Jun 2023Review(s) Completed, Editorial Evaluation Pending
21 Jun 2023Editorial Decision: Accept