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Hetero-structure Junctionless MOSFET with high-k corner spacer for high-speed and energy-efficient applications
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  • angsuman sarkar,
  • Mainak Mukherjee,
  • Niloy Ghosh,
  • Papiya Debnath,
  • Manash Chanda
angsuman sarkar
Kalyani Government Engineering College

Corresponding Author:[email protected]

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Mainak Mukherjee
Techno Polytechnic Durgapur
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Niloy Ghosh
Meghnad Saha Institute of Technology
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Papiya Debnath
Techno International New Town
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Manash Chanda
Meghnad Saha Institute of Technology
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In this research work, Hetero-structure Junction-less MOSFET having a Silicon-Germanium source and high-k inner corner spacer is proposed and investigated. In this article, we have shown that the introduction of a high-k dielectric material in the inner corner spacer and a low-k dielectric material in the rest of the spacer in the optimally designed device leads to a substantial reduction in parasitic capacitances, resulting in higher operating speed. It was also shown that proper doping in the drain-source underlaps regime, can improve the short channel performance (SCP) of the device by increasing the effective gate length. The optimally designed proposed device produces on current (ION) ~0.33 mA and off current (IOFF) ~5.55fA along with ION/IOFF=6.08x1010, Sub-threshold slope (SS)=59.6 mV/decade and drain induced barrier lowering (DIBL)=82.2 mV/V. This paper also highlights the performance improvement of the proposed device in terms of both speed and energy consumption, as compared to that of junctionless Double Gate MOSFET when implemented as logic gates.