Abstract

The present technology is scaling day by day which causes enormous leakage in power. For high-speed operation purpose, Random Access Memory chips are used as memory. Leakage power in the Gate and Sub - Threshold level is a serious issue in VLSI systems. Power of multiple architecture in an SRAM cell relies on each individual cell. The challenge will be to reduce leakage power in these cells. The 6T SRAM cell has some disadvantages such as power consumption, stability problems so, in order to overcome problem stated above different techniques in 7T transistors based SRAM structures are proposed, thus techniques like improved self -- controllable voltage and multi-threshold self -- controllable voltage is implemented in CMOS and FINFET Circuits using Cadence Tool.