Abstract

In this paper, a low-noise blocker-tolerant receiver that integrates Balun-LNA and N-Path mixer is proposed. Without on-chip balun, the LNA use a noise cancellation structure to constrain receiver noise. N-Path mixer and second-order low-pass TIA filter are used to implement the characteristics of blocker-tolerant. In 65nm CMOS process, the receiver occupies 0.09mm2 of active area, operates in the frequency range of 0.5--2 GHz and provides a 38dB conversion gain and a baseband bandwidth of 10 MHz. Consumes 29mW of power to achieve 2.8dB NF and 21.5dBm OOB-IIP3.