loading page

A 10GHz bandwidth 45.5dB SNDR buffer with local feedback in 45nm CMOS
  • +1
  • Jie Wu,
  • Qiao Meng,
  • Fei Li,
  • Yujia Huang
Jie Wu
Southeast University

Corresponding Author:[email protected]

Author Profile
Qiao Meng
Southeast University
Author Profile
Fei Li
Southeast University
Author Profile
Yujia Huang
Southeast University
Author Profile


A high speed and low power input/output buffer for time interleaving circuit is proposed in this letter. The buffer can be applied to high speed circuits operating at 20GS/s. This novel two-stage buffer is employed with bandwidth expansion and slew-rate enhanced techniques. An improved common-mode feedback circuit stabilizes the output common-mode voltage. This prototype buffer is fabricated in 45nm COMS process, and achieves 7.2bit ENOB at 10GHz input frequency with power consumption of 20.4mW, load of 0.3fF.
23 Nov 2022Submitted to Electronics Letters
23 Nov 2022Submission Checks Completed
23 Nov 2022Assigned to Editor
24 Nov 2022Reviewer(s) Assigned
01 Dec 2022Review(s) Completed, Editorial Evaluation Pending
04 Dec 2022Editorial Decision: Revise Minor
14 Dec 20221st Revision Received
14 Dec 2022Submission Checks Completed
14 Dec 2022Assigned to Editor
14 Dec 2022Review(s) Completed, Editorial Evaluation Pending
15 Dec 2022Editorial Decision: Accept