A high-voltage, external capacitor-less low-dropout regulator (HVLDO) with a transient enhancement loop is presented in this work. The proposed HVLDO is designed with high withstand voltage LDMOS transistors and a transient enhancement loop is proposed to properly inject or sink current to/from the gate and output nodes of the power transistors to achieve fast transient response under wide load range conditions and high stability. This HVLDO is fabricated in 0.5 μm SOI BCD process with an active area of 0.29 mm2. It operates over an input voltage range of 5.2 to 20 V, provides an output voltage of 5 V and a maximum load of 100 mA, while supporting load capacitances from 0 pF to 1 μF. Measurements show that this design has a line regulation of 0.88 mV/V and a load regulation of 0.22 mV/mA. The proposed HVLDO features fast line transient response of 60/20 mV@9.8 V/µs, fast load transient response of 30/70 mV@100 mA/µs, and recovery time of 2 µs without external capacitors. Compared with the prior art, this work achieves the best transient FOM of 12.19 fs.