Static random-access memory is a significant portion of digital system. The major problem of SRAM cell is the leakage of power. A shorted-gate fin-type field-effect transistor based SRAM cell design using leakage control transistor technique is proposed in this manuscript for minimizing the leakage power delay and power delay product. The proposed SG FinFETs based SRAM cell design using LECTOR technique is mainly used for stacking improvement to minimize the leakage power dissipation. LECTOR technique is mainly dependent on stacking of transistors, in which, two additional transistors are applied to lessen the leakage current and delay. The leakage control transistor utilizes two additional transistors are placed in series amid the pull up and pull down network that means additional SG FinFETs PMOS transistor inserts amid the pull up network and output terminal. The simulation of the proposed SGFinFETs based Static Random-Access Memory using LECTOR technique is in HSPICE simulation tool. Therefore, the proposed SGFinFETs based SRAM design using LECTOR method attains 11.31%, 51.47% and 45.46%, lower read delay, 44.44%, 26.33% and 33.45% lower write delay, 36.12%, 45.28% and 26.45% lower read power, 34.5%, 33.56%, 22.41% lower write power, 37.4%, 15.3% and 26.54% higher read SNM and 33.67%, 35.8%,12.09% higher write SNM compared to three existing methods.