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A Fast-Transient Output-Capacitorless LDO Regulator With Master-Slave Power Transistors
  • +4
  • Chenkai Hu,
  • Zhizhi Chen,
  • Shenglan Ni,
  • Qian Wang,
  • Xi Li,
  • Houpeng Chen,
  • Zhitang Song
Chenkai Hu
State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences, Shanghai, 200050, People’s Republic of China

Corresponding Author:[email protected]

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Zhizhi Chen
State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences, Shanghai, 200050, People’s Republic of China
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Shenglan Ni
State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences, Shanghai, 200050, People’s Republic of China
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Qian Wang
State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences, Shanghai, 200050, People’s Republic of China
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Xi Li
State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences, Shanghai, 200050, People’s Republic of China
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Houpeng Chen
State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences, Shanghai, 200050, People’s Republic of China
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Zhitang Song
State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences, Shanghai, 200050, People’s Republic of China
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Abstract

A fast-transient output-capacitorless (OCL) low-dropout (LDO) regulator with adjustable threshold push–pull stage (ATPS) and master-slave power transistors topology is presented in this paper. The ATPS consumes little quiescent current at light load current condition and the turn on threshold of the proposed ATPS can be adjusted by a current source. With the ATPS and master-slave power transistor topology, the proposed LDO can be stable from 0 to 100 mA load current at a maximum 100 pF parasitic load capacitance and a 0.7 pF compensation capacitor. It shows good figure of merit (FOM) without extra transient enhanced circuit. For the maximum 100 mA load transient with 100 ns edge time, the undershoot and overshoot are less than 33 mv.