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Simple yet efficient parallel signed multiplier design using radix-8 structure
  • Naga Venkata Vijaya Krishna Boppana,
  • Saiyu Ren
Naga Venkata Vijaya Krishna Boppana
Wright State University College of Engineering and Computer Science

Corresponding Author:vijay.krshn@gmail.com

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Saiyu Ren
Wright State University College of Engineering and Computer Science
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The continued quest for finding a low-power and high-performance hardware algorithm for signed number multiplication led to designing a simple and novel radix-8 signed number multiplier with 3-bit grouping and partial product reduction performed using magnitudes of the multiplicand and the multiplier. The pre-computation stage constitutes magnitude calculation and non-trivial computations required to generate partial products. A new partial product reduction strategy is deployed in the design to improve the speed with low cost. 8 X 8, 16 X 16, 32 X 32, and 64 X 64 designs are presented for the proposed architectures. Performance results include area, power, delay, and power-delay-product of synthesized and post-layout designs using 32 nm CMOS technology with 1.05 V supply voltage.
04 Feb 2023Submitted to The Journal of Engineering
08 Feb 2023Assigned to Editor
08 Feb 2023Submission Checks Completed
18 Feb 2023Reviewer(s) Assigned
25 Mar 2023Review(s) Completed, Editorial Evaluation Pending
26 Mar 2023Editorial Decision: Revise Major